Optimization of Test Pin-Count, Test Scheduling, and Test Access for NoC-Based Multicore SoCs

Abstract

We present the first pin-count-aware optimization approach for test data delivery over a network-on-chip (NoC). Our approach addresses the key issue of optimal utilization of the limited I/O resources provided by automated test equipment (ATE) to keep test time and test cost under control. By co-optimizing core test scheduling and pin assignment to access points, test cost can be lowered by reducing test time for a given pin budget, or by reducing the number of test pins without impacting test time. To further improve resource utilization, we consider the use of MISRs for compacting the test responses of embedded cores. We show how the optimization framework can be extended to include power constraints during test application. Experimental results for ITC'02 test benchmarks demonstrate that pin-count-aware co-optimization leads to shorter test times for a given pin-count budget and fewer pins for a given test-time budget. Comparisons with dedicated bus-based test-access mechanism designs and a baseline heuristic method are presented; our results demonstrate the benefits of the co-optimization method for NoC-based test access. The results also highlight the advantages of the proposed use of output compaction and the impact of power constraints on the optimized test schedule and test-access architecture.