Optimization of SiGe Graded Buffer Defectivity and Throughput by Means of High Growth Temperature and Pre-Threaded Substrates

Abstract

ABSTRACTDislocation glide kinetics dictate in relaxed graded buffers a fundamental opposition between the defectivity and throughput. For state-of-the-art Si-based applications, the trade-off between defect level and wafer cost (inversely related to throughput) has made the insertion of SiGe graded buffers into production difficult. We aim to mitigate the trade-off by reporting two advances that enable simultaneous improvements in both defectivity and throughput. The first is use of a high growth temperature to allow very fast dislocation glide velocities and growth rates as high as 1.0 μm/min. The second is the use of “pre-threaded” Si substrates, substrates with an elevated density of threading dislocations. By having dislocation nucleation controlled by uniformly distributed substrate threading dislocations, instead of unpredictable heterogeneous sources, impediments to dislocation glide, such as dislocation bundles and pile-ups, are reduced. By incorporating both advances into SiGe graded buffer epitaxy, dislocation pile-up densities are reduced by nearly three orders of magnitude, threading dislocation densities are reduced by a factor of 7.4×, and wafer throughput is increased at least 33%.