Optimization of process conditions of selective epitaxial growth for elevated source/drain CMOS transistor

Abstract

We studied the dependence of selective epitaxially grown silicon (SEG-Si) morphology under the conditions of ultrahigh vacuum chemical vapor deposition (UHV-CVD) by using a mixture of disilane (Si 2H 6) and chlorine (Cl 2) gases on Si(1 0 0) substrates patterned a complementary metal oxide semiconductor (CMOS) transistor. The SEG-Si surface became rougher with growth temperature, especially the SEG-Si in the p-MOS region, and there was a difference between p- and n-MOS regions in terms of SEG-Si thickness. It was revealed that an amorphous layer, which was induced by dry etching before SEG-Si growth, caused the roughness of the SEG-Si surface and difference in the thickness. Moreover, it was indicated that optimization of the growth conditions could sufficiently flatten the SEG-Si surface and correct the difference in thickness.