Leakage Current and Capacitance Reduction in CMOS Technology

Abstract

Prescribed performance is now regularly applied within the design of a chip, where it greatly contributes to improved predictability and platform robustness of complex systems, albeit a private complementary metal oxide semiconductor (CMOS) transistor uses little or no energy to extend speed. Because the number of transistors on a chip grow exponentially, the number of cores on the chip are still an important element used to stipulate performance. For choosing the output from among several inputs supported a get signal. Multiplexers are basic components in CMOS memory elements and data manipulation structures. Subthreshold conduction in a leakage mechanism is found between the source and the drain, between the gate and the substrate there is gate leakage, and between the source and the substrate and from the drain to the substrate there is junction leakage. For low-power application, leakage can be used with a 180-nm feature size. A CMOS transistor consumes power due to the leakage current in the idle condition. Dynamic logic engaged the data for limiting the time, the gate capacitance, and diffusion capacitance, which are also inbuilt in the transistor. If the width of the transistor increases proportionally, then diffusion capacitance also increases, and if the length of the transistor increases proportionally, then the gate capacitance also increases. Diffusion capacitance is better for making a layout perfect. This chapter consists of a projected leakage reduction technique to determine parasitic capacitance, which is solved with a statistical approach. This system will not implement a special type of multiplexer and arithmetic logic unit (ALU) with simulation on cadence software. Instead, a gate diffusion input (GDI) technique is used in multiplexers and ALU, compared GDI and CMOS techniques. The simulation shows that leakage current creates an 81% benefit and the facility consumption produces a 75% benefit. The number of gates in the GDI technique yields a 73% advantage. The capacitance calculation shows a 75% reduction in leakage current. These results are going to be very useful in improving the accuracy of and in developing an outsized signal model of metal oxide semiconductor field-effect transistors (MOSFETs).