Optimization of Pie-gate Bulk FinFET Structure

Abstract

In this paper we propose a novel Pie gate bulk FinFET structure for logic applications suitable for system-on-chip (SOC) requirements. The influence of gate at bottom to junction depth, misalignment was examined for deeper junctions and shallower junctions. It has shown that bulk FinFET with source/drain to body (S/D) junctions shallower than gate at bottom has equal or better subthreshold performance than SOI FinFET. Further, we extend the concept of heavy body doping in bulk FinFETs of Pie-gate structure. The characteristics of such bulk FinFET structure is analyzed by 3D device simulation and compared with SOI FinFET.