Abstract
This article presents the optimization of a one-transistor active pixel sensor (1T-APS), known as the photoelectron in-situ sensing device (PISD) built in a fully-depleted silicon-on-insulator (FD-SOI) substrate. By employing TCAD simulation, we develop a physics-based model and systematically investigate the impact of six key parameters – gate oxide thickness, buried oxide layer, top Si layer, gate length, length of active region, and substrate doping – on the device’s sensitivity and sensing range. Our comprehensive study provides guidance on the design of the PISD with the highest performance.
Highlights
Decades of extensive research have produced a number of mature and multifunctional image sensing technologies [1]–[3]
We have proposed a 1T-APS, named the photoelectron in-situ sensing device (PISD) [10], and demonstrated it experimentally in a 22 nm fully-depleted silicon-on-insulator (FD-SOI) technology [11]
By combining TCAD simulation with a simple analytical model, we have studied the effect of these parameters on the sensitivity and sensing range of the device
Summary
Decades of extensive research have produced a number of mature and multifunctional image sensing technologies [1]–[3]. Due to its small feature size, simplified structure and low power consumption, the 1T-APS promises a number of advantages over other photoelectron image sensors [4], [5]. The standard CMOS image sensor combines a photodiode with other transistors to realize random access, photodetection, and other functions, but suffers from a complicated cell structure [9]. To overcome these problems, we have proposed a 1T-APS, named the photoelectron in-situ sensing device (PISD) [10], and demonstrated it experimentally in a 22 nm FD-SOI technology [11]. The PISD integrates photo sensing, charge integration, buffer amplification, and random access in a 1T device without charge transfer or additional transistors
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