FDSOI technology and its implications for analog and digital design

Abstract

In this chapter, we start with an introduction of fully depleted SOI (FDSOI) technology by reviewing the FDSOI history followed by advantages and challenges in FDSOI manufacturing and design. Implementation of FDSOI technology in high-volume manufacturing (HVM) is then discussed along with the recent progress in improving FDSOI device performance and design for mobile applications. We then focus on the implications of FDSOI for digital and analog circuit design. The competition and augmentation of FDSOI with respect to other device architectures such as FinFETs are discussed. Finally, the technology roadmap for extending FDSOI beyond 10 nm in conjunction with future material and device innovations is proposed. CMOS scaling and FDSOI structure Since the first invention of the transistor in 1947 [1], the semiconductor industry has grown from a niche market into a multiple billion dollar business. The worldwide semiconductor revenue is expected to be more than $330 billion in 2014 [2]. The exploding growth of the semiconductor market is fueled by the seemingly endless innovations, particularly in CMOS technology, which replaced bipolar junction transistors around the 1980s and since then has become the cornerstone of semiconductor technology. As discussed in Chapter 1, the continued device miniaturization is the primary driving force behind the phenomenal growth of semiconductor technology. The evolution of semiconductor technology can probably be best described by Moore's Law [3] from the business perspective and by Dennard's scaling theory [4] from the device physics perspective. Moore's Law calls for a new technology node every 18 to 24 months by doubling device density, equivalently halving the cost per transistor with the assumption that the wafer substrate and process costs per wafer remain constant. Device scaling theory provides the guidance on scaling the critical device dimensions, such as gate length, gate oxide thickness, junction depth, doping concentration, device width, as well as the operating voltage, V DD . The device scaling theory predicts 30% reduction in active power at constant performance from node to node. Historical data is in good agreement with the prediction of scaling, although deviations do exist in recent technology nodes. For example, Figure 3.1 shows the thermal design power (TDP) as a function of clock frequency for a family of Intel i7 chips with the same number of cores and cache density. Scaling the same architecture from 45 nm to 32 nm results in roughly a 30% reduction in power, consistent with the scaling theory.