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Abstract
In this study on multi-nanosheet field-effect transistor (mNS-FET)—one of the gate-all-around FETs (GAAFET) in the 3 nm technology node dimension—3D TCAD (technology computer-aided design) was used to attain optimally reduced substrate leakage from options including a punch-through-stopper (PTS) doping scheme and a bottom oxide (BO) scheme for bottom isolation, with the performance improvement being shown in the circuit-level dynamic operation using the mNS-FET. The PTS doping concentration requires a high value of >5 × 1018 cm−3 to reduce gate induced drain leakage (GIDL), regardless of the presence or absence of the bottom isolation layer. When the bottom isolation is applied together with the PTS doping scheme, the capacitance reduction is larger than the on-state current reduction, as compared to when only the PTS doping concentration is applied. The effects of such transistor characteristics on the performance and capabilities of various circuit types—such as an inverter ring oscillator (RO), a full adder (FA) circuit, and a static random-access memory (SRAM)—were assessed. For the RO, applying BO along with the PTS doping allows the operating speed to be increased by 11.3% at the same power, or alternatively enables 26.4% less power consumption at the same speed. For the FA, power can be reduced by 6.45%, energy delay product (EDP) by 21.4%, and delay by 16.8% at the same standby power when BO and PTS are both applied. Finally, for the SRAM, read current (IREAD) increased by 18.7% and bit-line write margin (BWRM) increased by 12.5% at the same standby power. Through the circuit simulations, the Case 5 model (PTS doping concentration: 5.1 × 1018 cm−3, with BO) is the optimum condition for the best device and circuit performance. These observations confirm that PTS and bottom isolation applications in mNS-FETs can be utilized to enable the superior characteristics of such transistors to translate into high performance integrated circuits.
Highlights
Planar metal-oxide semiconductor field-effect transistors (MOSFETs) with single gates have scaled down over a long period of time according to Moore’s law and Dennard’s scaling rule
The 28T-full adder (FA) was designed using multi-nanosheet field-effect transistor (mNS-FET), and the performance optimization according to PTS doping and bottom oxide (BO) was analyzed with key figures of merit (FoM): dynamic power (Pdyn), energy-delay product (EDP), and delay
Static random-access memory (SRAM) was designed using mNS-FETs, and the performance optimization according to PTS doping and BO was analyzed with key figures of merit (FoM): static noise margin (SNM), read current (IREAD ), and bit-line write margin
Summary
Planar metal-oxide semiconductor field-effect transistors (MOSFETs) with single gates have scaled down over a long period of time according to Moore’s law and Dennard’s scaling rule. The fin height was gradually increased to obtain a larger effective width in the same footprint These methods of intensifying the FinFET design are close to their limits, such that multi-nanosheet field-effect transistor (mNS-FETs) will be used near the 3 nm Nanomaterials 2022, 12, 591. When three nanosheets are used in the mNS-FET structure, a channel is created in the substrate by the bottom gate (in addition to the nanosheet), which is a structure similar to a planar MOSFET Such a channel created in the lower substrate results in a high risk of leakage current in the 3 nm dimension. We believe that the results of this study will become guidelines for substrate engineering that enable leakage current to be reduced and optimal circuit performance to be achieved when designing 3 nm or smaller mNS-FET devices.
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