Optimization of Efficient LFSR Using Low-Power Techniques

Abstract

Power consumption plays an important role in digital circuits. One of the most energy consuming component is a flip-flop. The proposed work is based on reconfiguring the energy consumed component with an alternate circuit. The shift register reduces area and power consumption by replacing flip-flop with clock gating, pulsed latches and by Dual-pulse clock. Instead of using individual clock pulse, multiple parallel non-overlap delayed clock pulse is used to reduce the complexity of the circuit. The techniques explained above can be designed by using CMOS. It causes the power dissipation and degrades the speed of the circuit. Hence by using Dual-Pulse clock method, Complementary Pass Transistor Logic is used to reduce the power consumption and increase the speed of overall circuit. These techniques also attained the throughput of about 1500Kbps. The overall power consumption is compared for each case in different technologies. The Average Power, Maximum power, Power Delay and Area can be calculated with VDD=1.8V and fclk=1.4 KHz for different techniques. The simulation is performed using TANNER V13.0 and the analysis is carried out to show the effectiveness of proposed technique, which attains the power saving of about 98% and area up to 61% respectively.