Optimization of Dual-K Gate Dielectric and Dual Gate Heterojunction SOI FinFET at 14 nm Gate Length

Abstract

Modification of process parameters of the Fin shaped Field Effect Transistor (FinFET) is the field of research which has drawn attention after it has been inferred that these transistors diminish the leakage effects, which occur in planar transistors. The research paper presents a novel approach in which Artificial Neural Network (ANN) and Genetic Algorithm (GA) have been combined to optimize the structure of 14 nm Dual Gate Material Dual Gate Dielectric Material Heterojunction (DGMDGDM-Hetero) Silicon On Insulator (SOI) FinFET. The dataset mandatory for the training of ANN has been obtained through designing and simulating the DGMDGDM-Hetero SOI FinFET structure by varying the Si1-xGex height (H SiGe) and mole fraction (MF SiGe) in TCAD simulator. Through GA optimization, the optimal value of H SiGe and MF SiGe for which minimum Subthreshold Swing (SS), off-current (I d,off), Drain-Induced-Barrier-Lowering (DIBL) along with maximum on-current (I d,on) and I d,on–I d,off ratio achieved have been discovered. The considered FinFET structure was designed and simulated with optimal value of H SiGe and MF SiGe which resulted in ultimate best performance parameters. DIBL and leakage of 15.8 mV/V and 1.37 × 10−17A respectively, suggesting that DGMDGDM-Hetero SOI FinFET has more control over undesired Short Channel Effects (SCEs). Only 1.4% difference in the value of ANN-GA optimized and TCAD simulated performance parameters substantiate the effectiveness of optimization process.