Optimization of Design Parameters for Vertical Tunneling Based Dual Metal Dual Gate TFET

Abstract

In this paper, an optimally designed vertical tunneling based dual metal dual gate tunnel field effect transistor (DMDG-VTFET) is presented. The design parameters are chosen so as to fulfill the high-performance ON-state current of 1.33 μA, low standby power OFF-state current nearly 50.5 aA and Subthreshold Swing (SS) of 11 mV/decade. Moreover, the proposed TFET follows the International Technology Roadmap for Semiconductors (ITRS) roadmap for low standby power switch performance as ON current/ OFF current ratio (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> / I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> ) of the order of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> is obtained. Such results are attributed to the dominant carrier tunneling of the device which is in line with the gate electric field. This suppressed the lateral tunneling path which was responsible for the depreciation of the subthreshold slope, thus resulting in a super-steep subthreshold slope. By selecting appropriate work function on tunnel gate and auxiliary gate; I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> , I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> and threshold voltage V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> are significantly improved. Impact of epitaxial region height, source, channel, drain and epitaxial region doping concentration, spacer and dielectric material on ambipolarity of the device is thoroughly studied.