Optimization of CNFET Parameters for High Performance Digital Circuits

Shimaa Ibrahim Sayed,Mostafa Mamdouh Abutaleb,Zaki Bassuoni Nossair

doi:10.1155/2016/6303725

Abstract

The Carbon Nanotube Field Effect Transistor (CNFET) is one of the most promising candidates to become successor of silicon CMOS in the near future because of its better electrostatics and higher mobility. The CNFET has many parameters such as operating voltage, number of tubes, pitch, nanotube diameter, dielectric constant, and contact materials which determine the digital circuit performance. This paper presents a study that investigates the effect of different CNFET parameters on performance and proposes a new CNFET design methodology to optimize performance characteristics such as current driving capability, delay, power consumption, and area for digital circuits. We investigate and conceptually explain the performance measures at 32 nm technologies for pure-CNFET, hybrid MOS-CNFET, and CMOS configurations. In our proposed design methodology, the power delay product (PDP) of the optimized CNFET is about 68%, 63%, and 79% less than that of the nonoptimized CNFET, hybrid MOS-CNFET, and CMOS circuits, respectively. Therefore, the proposed CNFET design is a strong candidate to implement high performance digital circuits.

Highlights

CMOS technology faces significant challenges at the nanoscale due to several factors like short-channel effects, a lack of control over static leakage current and source-todrain tunneling [1, 2]
In order to sustain Moore’s Law, it is necessary to look for alternatives like Carbon Nanotube Field Effect Transistors (CNFETs) that have received a lot of attention in the past few years as a promising extension to silicon CMOS for future digital logic integrated circuits
Efforts have been made in recent years on modeling and simulating Carbon nanotubes (CNTs) related devices such as CNFET [11, 12] to evaluate the potential performance at the device level

Summary

Introduction

CMOS technology faces significant challenges at the nanoscale due to several factors like short-channel effects, a lack of control over static leakage current and source-todrain tunneling [1, 2]. In order to sustain Moore’s Law, it is necessary to look for alternatives like Carbon Nanotube Field Effect Transistors (CNFETs) that have received a lot of attention in the past few years as a promising extension to silicon CMOS for future digital logic integrated circuits. Carbon nanotubes (CNTs) are a promising material for flexible electronics which offer a wide variety of applications such as flexible solar cells, skin-like pressure sensors, and conformable RFID tags [4]. CNFET has many applications in digital circuits such as arithmetic circuits, Full Adder-Subtractor [5,6,7], and 6T SRAM [8] and there is hybridization between MOS and CNFET to improve performance for digital [9] or analog design [10]. Various optimized schemes are suggested and demonstrated to minimize the effect of parasitic capacitances and improve the speed of CNT ICs [13]

Methods

Results

Conclusion