Optimization of CMOS at Deep Cryogenic Temperatures

Abstract

Cryogenic CMOS is a sought-out technology because of its applications to fields like quantum computing and deep space exploration. Though slight advancements have been made within the field of cryogenic CMOS technology, there persists critical challenges that need to resolve to further advance the field. Hence, there is a need to solve challenges like understanding the undesirable effects due to the device physics at cryogenic temperatures such as high threshold voltage, kink-effects, abnormal subthreshold swing etc. and developing reliable circuit models because many rely on analytical modeling. The research models a NMOS ON-current and subthreshold slope at temperatures of 300K and 4K using Technology Computer-Aided Design (TCAD) by applying a single set of calibrated parameters. Additionally, detailing a proposed trap distribution model to reproduce abnormal subthreshold slope observed from 4K to 300K. The research also achieves to introduce an electron and hole mobility model for a wide temperature range since there has not been a unified model developed for silicon carriers from 4K to 300K. Lastly, the research aims to optimize MOSFETs at deep cryogenic temperatures by applying the calibrated parameters.