Optimally designed moderately inverted double gate SOI MOSFETs for low-power RFICs

Abstract

A design methodology to significantly enhance peak values of two key analogue/RF performance metrics-–gm2/Ids and gmfT/Ids—without degrading linearity metric (VIP3) in moderately inverted MOSFETs is demonstrated. An impressive improvement of 22% in gm2/Ids and more than twice in gmfT/Ids can be achieved by adopting optimal underlap source/drain (S/D) architecture instead of a conventional abrupt S/D design. Apart from the well-known reduction in the voltage gain (gm/gds), it is demonstrated that linearity degradation is expected to be a major bottleneck for scaling low-power and energy efficient devices into the nanometre regime. The optimal range of S/D profile parameters is identified by evaluating process and performance trade-offs associated with the underlap doping profile. A parameter sensitivity analysis shows that an optimally designed underlap S/D MOSFET exhibits greater tolerance to the variation of parameters as compared to conventional abrupt S/D devices. The results are significant for the design of low-power RFICs with advanced MOSFETs in emerging technologies.