Design and Simulation of SF-FinFET and SD-FinFET and Their Performance in Analog, RF and Digital Applications

Abstract

This paper presents TCAD simulation of Triple gate Step Fin FinFET (SF-FinEFT) and Step Drain FinFET(SD-FinFET) field effect transistor. The electrical characteristics of the devices are compared with conventional Fin-FET(cFinFET/FinFET). Various performance parameter like ON current Ion, leakage current Ioff, Ion/Ioff ratio, sub-threshold slope, DIBL have been observed. Also to check the device functionality in Analog, RF and Digital applications a comparative study of various parameters has been done between the proposed devices and conventional FinFET. We have used strained silicon as channel material for all the devices. As the number of transistors per square area on a chip keeps on increasing, the performance metrics for a planar MOSFET degrades and hence it faces various challenges in nano-meter regime. The need for a new device technology to control the unavoidable challenges was felt hence a 3-D Multi-gate transistor have emerged. These newer 3-D devices showed better performance in the nano meter regime. This paper analyzes parameters like the trans-conductance(gm), drain conductance (gd), trans-conductance generation factor, total gate capacitance (Cgg), cut-off frequency (ft), gain frequency product(GFP) for analog and RF performance. For digital application noise margin and propagation delay have been extracted.