Optimal Solution for VLSI Physical Design Automation Using Hybrid Genetic Algorithm

I Hameem Shanavas,R K Gnanamurthy

doi:10.1155/2014/809642

Abstract

In Optimization of VLSI Physical Design, area minimization and interconnect length minimization is an important objective in physical design automation of very large scale integration chips. The objective of minimizing the area and interconnect length would scale down the size of integrated chips. To meet the above objective, it is necessary to find an optimal solution for physical design components like partitioning, floorplanning, placement, and routing. This work helps to perform the optimization of the benchmark circuits with the above said components of physical design using hierarchical approach of evolutionary algorithms. The goal of minimizing the delay in partitioning, minimizing the silicon area in floorplanning, minimizing the layout area in placement, minimizing the wirelength in routing has indefinite influence on other criteria like power, clock, speed, cost, and so forth. Hybrid evolutionary algorithm is applied on each of its phases to achieve the objective. Because evolutionary algorithm that includes one or many local search steps within its evolutionary cycles to obtain the minimization of area and interconnect length. This approach combines a hierarchical design like genetic algorithm and simulated annealing to attain the objective. This hybrid approach can quickly produce optimal solutions for the popular benchmarks.

Highlights

Physical design automation has been an active area of research for atleast three decades
This work compares the performance of combined physical design automation tool for different benchmarks of physical design components
This iterative heuristic technique involves the combination of genetic algorithm (GA) and SA

Summary

Introduction

Physical design automation has been an active area of research for atleast three decades. When the physical design components like partitioning, floorplanning, placement, and routing are combined and optimized in terms of area, the cost increasing criteria like power and clock speed of each module can be controlled, and these subobjective criteria can be optimized to a further extent. Global optimization technique like genetic algorithm (GA) which captured the context of generation from biological system had been used for physical design problems like circuit partitioning, floorplanning, placement, and routing. This work proposes hybrid evolutionary algorithm to solve the graph physical design component problems This method includes several genetic algorithm features, namely, selecting population, performing crossover of the selected chromosomes, and if necessary mutation to get better stable solutions. The main objective of area optimization and interconnect length reduction can be achieved by incorporating hybrid evolutionary algorithm (HEA) in VLSI physical design components

Graphical Representation of Physical Design Components

Global Optimization Using GA

Local Optimization Using SA

Optimization by Simulated Annealing

Experimental Results

Conclusion