Optimal Retiming of Multi-Phase, Level-Clocked Circuits

Abstract

Abstract : Using level-sensitive latches instead of edge-triggered registers for storage elements in a synchronous system can lead to faster and less expensive circuit implementations. This advantage derives from an increased flexibility in scheduling the computations performed by the circuit. In edge-clocked circuits the amount of time available for the computation between two registers is precisely the length of the clock cycle, while in circuits using level-sensitive latches a computation can borrow time across latches thus reducing the amount of dead time in the clock cycle. In either type of circuit, achieving maximum performance requires locating the storage elements in such a way as to spread the computation uniformly across a number of clock cycles. Retiming is the process of rearranging the storage elements in a circuit to reduce the cycle time or the number of storage elements without changing the interface behavior of the circuit as viewed by an outside host. Retiming in effect reschedules the circuit computations is time based on the length of those computations. In this paper, we extend the retiming techniques developed for edged-clocked circuits by Leiserson. Rose and Saxe to a general class of multi-phase, level-clocked circuits. We first describe this class of well-formed circuits and define what it means for a well-formed, level-clocked circuit to operate correctly. We then show that a set of constraints can then cbe used to retime a level-clocked circuit using efficient integer linear programming techniques similar to those used for edge-clocked circuits.