Peak Power Optimizations

Abstract

In hardware generated using CAOS, concurrent execution of maximal set of actions in each clock cycle reduces the latency (number of clock cycles) of the design at the cost of increase in its peak power, which is defined as the maximum instantaneous power (due to switching activity) during one clock cycle. In Chapter 5, various heuristics targeting the minimization of peak power in designs generated from CAOS are proposed. The peak power heuristics presented in that chapter postpone some actions (among all the actions that can be executed in a clock cycle) to the future clock cycles for peak power reduction. Also, actions which were postponed in the previous clock cycles are considered for execution in the present clock cycle. For this, those heuristics propose the use of extra state elements in order to remember which actions were postponed in the previous clock. The main drawback of those approaches is that such a use of extra state elements is associated with the corresponding area and power overheads.