Optimal Nano-Dimensional Channel of GaAs-FinFET Transistor

Abstract

This paper investigates the optimal nano-dimensions channel for Gallium Arsenide Fin Field Effect Transistor (GaAs-FinFET) based on I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ratio and subthreshold swing (SS). The impact of reducing channel dimensions (length, width, and oxide thickness) on GaAs-FinFET performance has been evaluated in terms of various electrical characteristics (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> , SS, VT and DIBL). The MuGFET simulation tool is used in this study to simulate the current-voltage characteristics for different dimensions of channel. According to highest I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ratio, and nearest SS to the ideal SS, the best channel dimensions of GaAs-FinFET are designed. The results show that the best performance can be achieved with the lowest scaling factor, K of 0.25, when the length is 40 nm, the width is 3 nm, and the oxide thickness is 1 nm.