Optimal Global Interconnects for Networks-on-Chip in Many-Core Architectures

Abstract

While integrated circuits are moving toward many-core architectures, no circuit-aware interconnect technology optimization methodology has been reported for such chips. To utilize a many-core chip to its full potential, low-latency ultrahigh-bandwidth intercore interconnects are needed. In this letter, for the first time, interconnect dimensions in a network-on-chip (NoC) are optimized to achieve large bandwidth density and small latency simultaneously. The optimal wire width for a NoC is found to be more than ten times smaller than the previously obtained optimal global interconnect width. For a 1000-core chip implemented in the technology year 2015, the optimal wire width is found to be minimum-dimension limited.