System-on-a-chip global interconnect optimization

Abstract

The width of global interconnects is optimized to have a large bisectional bandwidth along with a small latency, power dissipation, repeater area and via blockage. The optimal wire width, which maximizes the product of data flux density OD and reciprocal delay 1//spl tau/, is independent of the interconnect length and can be used for all global interconnects. Data flux density OD (per unit width) determines the bisectional bandwidth and therefore, the total number of bits per second that global interconnect levels can potentially transfer. Using optimal wire width decreases the latency, energy dissipation, and repeater area by 42%, 30%, and 84%, respectively compared to using half the optimal wire width at the price of 14% smaller bisectional bandwidth.