OPT-VCG: A Novel Proposal for 3D SoC Test Optimization

Abstract

As an emerging technology for on-chip interconnect scaling in vertical direction in semiconductor industry, through-silicon-via (TSV) demonstrates its advantages and has been adopted for 3D SoC implementation. Optimal test architecture and test scheduling are significant for stacked 3D SoC design. However existing design methods cannot achieve both optimal test time and individual rationality. In this paper, game theory based 3D SoC test architecture optimization and test scheduling method is proposed under constraints of the available number of TSVs for test time minimization and rational test band width allocation. VCG algorithm is brought to 3D SoC design. Three kinds of stacked SoCs are built using ITC’02 SoC test benchmarks, and experimental results on them show the advantages of the proposed method over prior work.