Optimization of Test Wrapper for TSV Based 3D SOCs

Abstract

Embedded core-based three dimensional system-on-chip (3D SOC) is a new design paradigm in modern semiconductor industry. For testing of these 3D SOC efficient testing techniques are required and designing the test wrapper of core is also an important issue in this respect. In this paper we have addressed a 1500-style wrapper optimization in 3D ICs based on Through Silicon Vias (TSVs) for vertical interconnects. It is assumed that the core elements are spanned over several layers of 3D ICs. Here we are trying to design the wrapper that reduces the testing time of the core. This work is intended to design balanced wrapper chains using available TSVs as there are an upper limit on the total number of TSVs due to small chip area. We propose a polynomial time algorithm of O(N) where N is number of wrapper elements to design the wrapper. Obtained results are presented based on the ITC'02 SOC test benchmarks. The results demonstrate that our algorithm has better performance with respect to both TSVs utilization and test time for higher TAM width compared to [10].