Abstract
The multiple transition fault model has been used to represent alternative defective gate combinations in the circuit. However, the number of faults is very large even of modest size circuits and therefore the defective configuration may not be considered. It is shown that multiple transition faults can be stored compactly in Binary Decision Diagrams. Furthermore, important operations for identifying the location of failures are implemented without fault enumeration. Experimental results on some of the largest ISCAS’85, ISCAS’89. and ITC’99 benchmarks demonstrate the scalability of the proposed method.
Highlights
With the technology moving to nanometer regime, the task of testing and diagnosing failures in integrated circuits (ICs) has become very demanding
The process of identifying the location of failures in an IC is guided by a set of possible fault sites [1]
This process is guided by a set of possible fault sites in the IC called suspects
Summary
With the technology moving to nanometer regime, the task of testing and diagnosing failures in integrated circuits (ICs) has become very demanding. Methods like [2]-[3] are restricted to a single defect location. This is very unlikely to be the case in deep submicron. The transition fault model [9] is used, but the authors assume that only one fault is being generated at each node This is rarely the case in deep submicron. This may turn out to be a restriction that may misguide the identification of the location of failures. This paper uses the multiple transition fault model (MTF) along sensitized paths to represent alternative defective gate combinations in the circuit.
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