OPC-Lite for gridded designs at low k1

Abstract

Highly regular gridded designs are generally seen as a key component for continued advances in lithographic resolution in a time of limited further progress in lithography hardware [1]. With a given process technology tool set, higher pattern density (lower k1) and quality are achieved using gridded design rules (GDR) in comparison to conventional 2D designs. GDR is necessary for designs with k1 approaching the theoretical limit ∼ 0.25. A highly effective implementation of GDR is the lines+cuts approach discussed in [4, 5, 8] and else- where. Excellent results at very advanced nodes are achieved by this double-patterning process, where lines are created first, then cuts are patterned on top as required by circuit connectivity. The regular structure of gridded designs offers the opportunity to use an optimized approach to Optical Proximity Correction (OPC), one taking full advantage of the design style to achieve best possible ac- curacy and speed and at the same time small mask file size and good manufacturability. In this work we describe our GDR-tailored OPC tool called OPC- Lite [6]. The OPC-Lite approach is discussed and compared to conventional 2D OPC. Sub-20nm silicon data are shown, validating predictive quality of our simulation and OPC techniques.