Lithography process design for 4-Gb DRAM of 0.31 K1 with KrF

Abstract

We studied lithography process of 0.31 k1 for DRAM device with KrF light source. DRAM device with 100 nm half-pitch design rule, which can facilitate 4 Giga-bit in a chip, can be patterned with the aid of super resolution enhancement techniques (SRET) and high NA (equals0.7) KrF scanner. The SRET includes the use of strong off-axis illumination (OAI) and attenuated phase shift mask (8% transmittance). In the case of using the SRET, those of very large iso-dense (I-D) bias from the optical proximity effect (OPE), narrow depth of focus (DOF) of (semi-) isolated features and existence of dead-zone in the peripheral circuit and so forth, are emerging as critical issues to be solved except the very fundamental lens aberration. These problems can only be solved when aggressive optical proximity correction (OPC) techniques such as selective bias and assistant feature to (semi-) isolated features are used for every critical layer of the device, where the OPC rules were generated from simulations and empirical experiments. Besides OPC techniques, close and cooperative approach of lithographers and designers is also necessary for the process oriented layout design especially to avoid the dead-zone that SRET generates. We have tried to customize the lithography process design for 0.31 k1 and finally obtained the common process latitude to make the full 4 Giga-bit DRAM device lithography feasible on this basis.