ONOFIC Pull-Up Approach in Domino Logic Circuits Using FinFET for Subthreshold Leakage Reduction

Abstract

In this paper, ON/OFf logIC (ONOFIC) approach is applied in pull-up network of domino Fin Field-Effect Transistor (FinFET) gates. With this approach, 2-, 4-, 8- and 16-input OR gates are simulated with 32-nm FinFET technology node and compared with standard footless domino gate and LECTOR-based domino gate. In LP mode, proposed ONOFIC pull-up domino gates reduce subthreshold leakage power up to 21.9% compared to standard footless domino gates and reduce by 2.04–40.2% compared to LECTOR-based domino gates at 25 °C. At 110 °C, proposed ONOFIC pull-up domino gates reduce subthreshold leakage power up to 17.8% compared to standard footless domino gates and reduce up to 41.7% compared to LECTOR-based domino gates. In SG mode, proposed ONOFIC pull-up domino gates reduce subthreshold leakage power by 8.1% compared to standard footless domino gates and reduce by 60.4–69.5% when compared to LECTOR-based domino gates at 25 °C. At 110 °C, proposed ONOFIC pull-up domino gates reduce subthreshold leakage power up to 11.3% compared to standard footless domino gates and reduce by 44.8–66.9% compared to LECTOR-based domino gates.