On-chip charge pump design for 3D non-volatile flash memory: from industry perspective

Abstract

Power density of integrated circuits rises exponentially with the introduction of each new generation of technology as a direct result of Moore's law. High throughput consumer electronics applications with intricate functionality and computationally demanding circuitry further enhance power density. Despite this continuous trend of incremental power density over time, low power became a common need for circuits in memory domain. The challenges and methods of constructing an on-chip low-power energy harvesting block for 3D Non-volatile memory are discussed in this work. The topic and methods described in this work center on developing a smaller-area, higher-efficiency on-chip charge pump design to keep up with Moore's law of transistor scaling every two years. To achieve this, charge pump design metrics including criteria for sizing of pump capacitance, boost circuit capacitance, and pass-gate are examined in detail. The principles of charge sharing, boost-time consideration, bootstrap, pre-charge for Vth cancellation, and charge transfer have all been thoroughly discussed to achieve higher efficiency. This study also presents design methods of initializing of internal pump nodes to boost charge transfer. The optimal circuit placement inside the die was also discussed to maximize benefits from power bussing. Finally, proven industrywide pump design guidelines are discussed and presented in every section. Device characteristics and hspice simulations are used to support design criteria that were discussed. The study offers an overview of the recommendations for most recent small area, low power, on-chip charge pump design for non-volatile memory products.