On-chip ADC for infrared focal plane arrays

Abstract

This paper presents a low power and small area analog-digital converter (ADC) for infrared focal plane arrays (IRFPA) readout integrated circuit (ROIC). Successive approximation register (SAR) ADC architecture is used in this IRFPA readout integrated circuit. Each column of the IRFPA shares one SAR ADC. The most important part is the three-level DAC. Compared to the previous design, this three-level DAC needs smaller area, has lower power, and more suitable for IRFPA ROIC. In this DAC, its most significant bit (MSB) sub-DAC uses charge scaling, while the least significant bit (LSB) sub-DAC uses voltage scaling. Where the MSB sub-DAC consists of a four-bit charge scaling DAC and a five-bit sub-charge scaling DAC. We need to put a scaling capacitor Cs between these two sub-DACs. Because of the small area, we have more design methods to make the ADC has a symmetrical structure and has higher accuracy. The ADC also needs a high resolution comparator. In this design the comparator uses three-stage operational amplifier structure to have a 77dB differential gain. As the IR focal plane readout circuit signal is stepped DC signal, the circuit design time without adding the sample and hold circuit, so we can use a DC signal instead of infrared focal plane readout circuit output analog signals to be simulated. The simulation result shows that the resolution of the ADC is 12 bit.