On Using On-Chip Clock Tuning Elements to Address Delay Degradation Due to Circuit Aging

Abstract

Lifetime performance of digital integrated circuits degrades as a consequence of circuit aging. In the past few years, there has been extensive research to reduce the impact of aging by different design techniques, or to predict the degradation and adapt the circuit accordingly. In this paper, we explore a novel perspective to this problem by exploiting the presence of clock tuning elements in high-performance designs. By combining on-chip sensors to predict setup or hold-time violations with the clock tuning elements, we provide an effective self-tuning mechanism for each circuit sample. The proposed method can operate in-system to prolong the circuit's maximum performance in its unique operating environment.