On the VLSI Energy Complexity of LDPC Decoder Circuits

Abstract

Sequences of randomly generated bipartite configurations are analyzed; under mild conditions almost surely such configurations have minimum bisection width proportional to the number of vertices. This implies an almost sure $\Omega (n^{2}/d^{2}_{\mathrm {max}})$ scaling rule for the energy of directly-implemented low-density parity-check (LDPC) decoder circuits for codes of block length $n$ and maximum node degree $d_{\mathrm {max}}$ . It also implies an $\Omega (n^{3/2}/d_{\mathrm {max}})$ lower bound for serialized LDPC decoders. It is also shown that all (as opposed to almost all) capacity-approaching, directly-implemented non-split-node LDPC decoding circuits, have energy, per iteration, that scales as $\Omega \left ({\chi ^{2}\ln ^{3} \chi }\right )$ , where $\chi =(1-R/C)^{-1}$ is the reciprocal gap to capacity, $R$ is code rate, and $C$ is channel capacity.