Abstract
We present a theory and design techniques for polynomial division circuits with the primary focus on testing of digital and mixed-signal devices. We estimate the aliasing rate for the proposed circuits (signature analyzers) and show how to improve it. Two types of design techniques are examined for mixed-signal circuit analyzers that are arithmetical by nature. The techniques are scalable and valid for an arbitrary size and base of the number system. The proposed devices have both low hardware complexity and aliasing rate. The design techniques and devices can also be used in general arithmetic/algebraic error-control coding, cryptography, digital broadcasting and communication.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.