On the modeling and testing of gate oxide shorts in CMOS logic gates

Abstract

The electrical and logic operation of CMOS simple logic gates in the presence of gate oxide shorts is analyzed using realistic defect models. These models reflect the resistive nature of gate oxide shorts and the difference between n- and p-channel transistors. The resistance of a short plays a central role in determining the actual circuit behavior. Faults caused by gate oxide shorts can be dependent not only on inputs to the gate containing the fault but also on other signals in the circuit, and can escape tests generated using normal TPG schemes. The stuck-at test set for a logic gate cannot guarantee to detect all transistor gate-to-source and gate-to-drain shorts in the logic gate. Gate oxide shorts in n-channel transistors affect circuit operation more severely than those in p-channel transistors do. Some limitations of present transistor-level fault modeling techniques are revealed. >