Abstract
In this paper, a heuristic methodology for design of highly linear MOSFET capacitors (MOSCAPs) has been presented. For a certain amount of accessible chip area, the proposed algorithm intends to find the structure which has the least C-V variation. It uses a modified version of the genetic programming to optimize the capacitor topology and transistors' dimensions. To test the performance of the algorithm, it was utilized for obtaining a highly linear 1 pF capacitor, i.e. with less than 3% variation of capacitance versus 1 V variation across the MOSCAP structure terminals, in a commercial 0.18 mum standard digital CMOS technology. This level of linearity can be otherwise achieved only with MIM capacitors, which are not available in digital CMOS processes.
Sign-in/Register to access full text options 
Free) 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
