Mixed analog-digital design considerations in deep submicron CMOS technologies.

Abstract

Higher speed and higher density are the main thrusts of CMOS technology and are achieved by device miniaturization. In deep submicron geometries, the supply voltage is scaled down to prevent reliability hazards such as oxide breakdown and hot carrier effects and also to reduce energy per operation of digital circuits. Lowering the supply voltage directly reduces the signal swing, which in turn makes the design of high-speed wide dynamic range mixed-signal SC circuits a challenge. It is also desirable to implement SC circuits in a standard digital CMOS process, where double-poly capacitors are not available, because the driving forces behind the CMOS technologies are DRAMs and microprocessors which do not require linear capacitors. This thesis demonstrates that analog circuit design can track projected digital technology until at least the year 2010. It addresses the design of low-voltage and high-speed SC circuits and also explores the feasibility of using MOSFET capacitors in a linear SC circuit. The thesis describes an experimental CMOS process implemented as a subset of a μm dual n+/p+ poly gate process using natural MOSFETs. A experimental SC sigma-delta modulator is presented—the lowest supply voltage reported so far for SC Σ∆ modulators. Also described is a high-speed fourth-order SC bandpass Σ∆ modulator and a novel fourth-order double-sampled SC bandpass Σ∆ modulator together with their experimental results. Finally, a fourth-order bandpass SC Σ∆ modulator designed in a digital CMOS process using pMOSFET capacitors is described. 1 V 0.5 1 V