Abstract
This brief presents a detailed analysis on DAC-based current drivers implemented with bipolar technology. In many power applications, the need of speed and driving capability leads to the choice of bipolar transistors as driving elements, but such devices can suffer linearity issues in high accuracy applications. A method of discussion for such architectures is introduced, and the related analytical model provides a fast estimation of the linearity performances, favoring the choice of a convenient block floor-planning and an effective scrambling strategy. The theoretical computations are, then, compared with transistor level simulations results and, finally, validated by measurements, carried out on a circuit implementation manufactured in a 130-nm BiCMOS technology.
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