On the Impact of Time-Zero Variability, Variable NBTI, and Stochastic TDDB on SRAM Cells

Abstract

We propose a Monte Carlo (MC) simulation framework for circuits taking into account the time-dependent dielectric breakdown (TDDB) statistics along with time-0 variability and variable negative-bias temperature instability (NBTI) under circuit operating conditions in SPICE environment. MC simulation is performed with the proposed framework for $\sim 100\text{k}$ static random access memory (SRAM) cells using experimentally calibrated device-level degradation distribution. Cell performance degradation is compared for both planar and FinFET-based SRAM cells. It is shown that TDDB can significantly impact the SRAM failure probability even under usual circuit operation. It is reported that FinFET-based cells show far more robustness toward cell performance degradation than their planar counterparts.