Abstract
Different origination theories for squat-type rail defects are examined and confronted with experimental evidence. Based on the morphology of the three-dimensional defect crack pattern, with a leading crack directivity governed by the tangential stress history, it is shown that theories assuming dynamic wheel-rail interaction as a direct initiation mechanism of the double-lobed defect violate the causality principle. Rail surface anomalies of three categories increase the tangential stress exposure and thus the risk of defect development: pertaining to the material properties, contact geometry (including both the global scale, involving the dynamic stress level transmitted by the contact area, and the local scale, involving transient stress redistribution within this area), and contact stiffness. Both detection measures focusing on geometrical surface deviations giving rise to dynamic wheel-rail interaction (such as axle-box acceleration measurements) and the idea of a critical diameter for such imperfections are inadequate. Instead, and apart from the surface geometry, steel micro-cleanliness and chemical composition, phase transformation mechanisms of surface material (due to operational conditions or treatment by grinding or milling) and welding deserve attention. Fluid entrapment remains a potentially contributing factor in early growth, while crack face oxidation and corresponding volumetric expansion may contribute at any stage after initiation.
Highlights
Si technology faces fundamental limitations due to ever-reducing gate lengths and the consequent decreased gate controllability.[1]
Using a compact analyzing model and structural advantages, we introduce an excellent and optimized performance of hexagonal boron nitride (h-BN) dual-gated ReS2 having a high mobility of 46.1 cm2V-1s-1, a high current on/off ratio of ~106, a subthreshold swing of 2.7 Vdec-1, and a low effective interface trap density (Nt,eff) of 7.85 ×1010 cm-2eV-1 at a small operating voltage (< 3 V)
Field-effect transistors (FETs) using ReS2 as a channel have been widely reported, their performance is inferior to those of MoS2, because ReS2 field-effect transistors (FETs) have low mobility, low current on/off ratio, and large subthreshold swing.[16]. To overcome this low performance, h-BN was used as a gate dielectric, graphene contact or suspended structure were designed for nextgeneration devices.[17,18]
Summary
Si technology faces fundamental limitations due to ever-reducing gate lengths and the consequent decreased gate controllability.[1]. Since TMD materials like ReS2 have a large surface/volume ratio, the interface between the TMD channel and the gate dielectrics affects the performance of the devices significantly.[19,20,21] usage of a h-BN gate dielectric,[22] which has almost no dangling bonds acting as charge carrier traps, or a dual-/tri- gated structure[23] to increase gate controllability, can lead to an improvement in the performance of FETs
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