On the feasibility of SISO control-theoretic DVFS for power capping in CMPs

Abstract

Power capping are increasingly being deployed in modern processors to meet performance/power requirements of new workloads. These computing systems are limited in their power dissipation, demanding a dependable power management scheme to guarantee the system’s efficiency and dependability. Although several ad-hoc and heuristic power management approaches can be found in the literature, their main shortcoming is the lack of formal guarantees to ensure dependability of the processors. Control-theoretic approaches promise flexibility and robustness for DVFS strategies. However, the creation of a responsive yet stable controller requires the often neglected tasks of proper system identification and performance analysis for target applications. This paper presents dependability evaluation of Single-Input Single-Output (SISO) controllers for power capping on single-core as well as multi-core processor architectures. We evaluate responsiveness of different class of applications to computer system control inputs (i.e., DVFS). We illustrate the feasibility of SISO controllers for power capping using the Sniper simulator running PARSEC, SPLASH2 and a set of custom microbenchmarks. Based on our observations, we provide guidelines for developing stable and robust SISO controllers for power capping, show the scenarios where simple classic SISO controllers might not be effective, and identify early symptoms that may result in instability for power capping controllers.