On the Feasibility of Nanoscale Triple-Gate CMOS Transistors

Abstract

The feasibility of triple-gate MOSFETs (TGFETs) for nanoscale CMOS applications is examined with regard to short-channel effects (SCEs) and gate-layout area. Three-dimensional numerical simulations of TGFETs reveal that much more stringent body scaling for SCE control is needed for undoped bodies relative to doped ones (which are not viable for nanoscale devices) due to the suppression of corner current conduction (which is technologically advantageous) in the former. When the undoped body is scaled for adequate SCE control, further analysis shows that the generic TGFET suffers from severe layout-area inefficiency relative to the fully depleted single-gate SOI MOSFET (FDFET) and the double-gate (DG) FinFET, and the inefficiency can be improved only by evolving the TGFET into a virtual FDFET or a virtual DG FinFET. We suggest then that the TGFET is not a feasible nanoscale CMOS transistor, and thus the DG FinFET, which is more scalable than the FDFET, seems to be the most promising candidate for future CMOS applications.