Abstract
Existing methodologies for determining gate delay fault coverages are shown to have certain deficiencies. A new and more realistic delay model is presented with the ultimate goal of ensuring error-free circuit operation through obtaining true fault coverages that extend upto the actual slacks. Methods are given that achieve such coverages when possible. Results of experiments performed to evaluate the practical benefits of the proposed methods over previous approaches are given. The proposed method over previous approaches are given. The proposed method based on varying the sampling time of the circuit outputs during testing is seen to produce very high delay fault coverages upto the actual circuit slacks, as opposed to methods based on fixed output sampling times.
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