Correlation-reduced scan-path design to improve delay fault coverage

Abstract

Experimental data is presented for eleven benchmark circuits to show how test pattern correlation in a scan-path design circuit adversely affects delay fault coverage, and to demonstrate that most undetected delay faults caused by the test pattern correlation are close to latch outputs. Topology-based latch correlation measures are introduced and used by a companion latch arrangement algorithm to guide the placement of latches in a scan-path design, with the objective of minimizing the effect of the test pattern correlation and maximizing the delay fault coverage. Experimental results with benchmark circuits indicate that the scan-path found by the algorithm clearly achieves better delay fault coverage than a scan-path having no deliberate arrangement, and, in fact, achieves nearly the coverage that can be gotten by unrestricted application of the test vectors to the circuit without a scan-path. The data also indicates that the algorithm is most effective in covering delay faults that are located nearest the latch outputs of the circuit. The approach has an advantage over other arrangement schemes in that it is simple to implement and does not require significant computational time even for large circuits. CPU-time and memory required by this algorithm to find an optimal latch arrangement may increase exponentially with the circuit size. Consequently, a more efficient algorithm is sought. In this paper, we fvst present experimental data for eleven benchmark circuits to show how latch correlation affects the delay fault coverage in a scan-path design circuit. The experiment demonstrates that latch correlation adversely affects delay fault coverage. and that most undetected delay faults caused by the test pattern correlation are close to latch outputs. We then introduce topology-based latch correlation measures to guide the placement of latches in a scan-path design with the objective of minimizing the effect of the test pattern correlation and maximizing the delay fault coverage. We also develop a latch arrangement algorithm that uses the proposed latch correlation measures. Experimental results with eleven benchmark circuits indicate that the scan-path found by the algorithm clearly achieves better fault coverage than a scan-path having no deliberate arrangement. and, in fact, achieves nearly the coverage that can be gotten by unrestricted application of the test vectors to the circuit without a scan-path.