On the Design of Efficient Residue-to-Binary Converters

Abstract

Residue-to-binary (R/B) converter plays a pivotal role in various computer arithmetic circuits and cryptographic applications. In this paper, efficient hardware implementation of R/B converters have been reported for the moduli set of (2n-1,2n,2n+1) and (2n-1,2n,2n+1). The functionality of the theorems have been verified using VHSIC (Very High Speed Integrated Circuit) hardware description language (VHDL) and synthesized using Xilinx ISE in the device xc6vlx760ff1760-1. Performance parameters have been compared as a function of propagation delay (ns), power (nW) consumption and FPGA resource utilization. The simulations were carried out for three different values of n. Simulation results also offered the pros and cons of the above mentioned parameters.