Abstract
Neuromorphic systems have shown improvements over the years, leveraging Spiking neural networks (SNN) event-driven nature to demonstrate low power consumption. As neuromorphic systems require high integration to form a functional silicon brain-like, moving to 3D integrated circuits (3D-ICs) with three-dimensional network on chip (3D-NoC) interconnect is a suitable approach that allows scalable design, shorter connections, and lower power consumption. However, highly dense neuromorphic systems also encounter the reliability issue where a single point of failure can affect the systems’operation. Because neuromorphic systems rely heavily on spike communication, an interruption or violation in the timing of spike communication can adversely affect the performance and accuracy of a neuromorphic system. This paper presents NASH, a a fault-tolerant 3D-NoC based neuromorphic system that incorporates as processing elements, lightweight spiking neuron processing cores (SNPCs) with spike-timing-dependent-plasticity (STDP) on-chip learning. Each SNPC houses 256 leaky integrate-and-fire (LIF) neurons and 65k synapses. Evaluation results on MNIST classification, using the fault-tolerant shortest-path K-means-based multicast routing algorithm (FTSP-KMCR), show that the NASH system can maintain high accuracy for up to 30% permanent fault in the interconnect with an acceptable area and power overheads when compared to other existing systems. a This project is supported by the University of Aizu, Competitive Research Funding (CRF), Ref. UoA-P6-2020
Highlights
Spike based neuro-inspired computing has gradually gained awareness both to provide better insight into the brain’s computation and to explore this computation through event-driven neuro-inspired systems
The rest of the routing is done from the selects a node (SP node) to the destination nodes. The efficiency of such 3D mesh topology given a randomly connected (RNDC) Spiking neural networks (SNN) and multicast algorithm can be determined by the distance from source to destination, the efficient bandwidth, the average spike rate (SR) and the maximal spiking frequency described in equations 1-6 which are expressed in [40] as: The total number of functional link given as: TL = 3(1 − α) 3 n2(√3 n − 1)
To avoid violation of the spike timing rule due to faulty links in the network, we proposed in our previous work [10] a fault-tolerant k-means based multicast routing algorithm (FT-KMCR) and a fault-tolerant shortest path k-means based multicast routing algorithm (FTSP-KMCR)
Summary
Spike based neuro-inspired computing has gradually gained awareness both to provide better insight into the brain’s computation and to explore this computation through event-driven neuro-inspired systems. There is a need for a densely parallel architecture with low-power consumption, light-weight spiking neuro processing cores (SNPCs) with on-chip learning, and efficient neuro-coding scheme Another major hurdle that needs to be surmounted is the on-chip neurons communication and spike routing. We need to consider that the number of neurons to be connected are magnitudes of times larger than the number of cores that need to be interconnected on recent multicore system on chip platforms [14] These hurdles make the building of such a neuromorphic integrated circuit (IC) a challenging task [15]. (c) 3D neuromorphic architecture with through silicon vias (TSVs) for vertical inter-layer connection capable of supporting the high level of connectivity required for the vision task mapped according to the partitions in (b) This image is inspired by the work in [10].
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