Architecture and Design of a Spiking Neuron Processor Core Towards the Design of a Large-scale Event-Driven 3D-NoC-based Neuromorphic Processor

Mark Ogbodo,Khanh Dang,Abderazek Abdallah,Fukuchi Tomohide,D Roy

doi:10.1051/shsconf/20207704003

Abstract

Neuromorphic computing tries to model in hardware the biological brain which is adept at operating in a rapid, real-time, parallel, low power, adaptive and fault-tolerant manner within a volume of 2 liters. Leveraging the event driven nature of Spiking Neural Network (SNN), neuromorphic systems have been able to demonstrate low power consumption by power gating sections of the network not driven by an event at any point in time. However, further exploration in this field towards the building of edge application friendly agents and efficient scalable neuromorphic systems with large number of synapses necessitates the building of small-sized low power spiking neuron processor core with efficient neuro-coding scheme and fault tolerance. This paper presents a spiking neuron processor core suitable for an event-driven Three-Dimensional Network on Chip (3D-NoC) SNN based neuromorphic systems. The spiking neuron Processor core houses an array of leaky integrate and fire (LIF) neurons, and utilizes a crossbar memory in modelling the synapses, all within a chip area of 0.12mm2 and was able to achieves an accuracy of 95.15% on MNIST dataset inference.

Highlights

Neuromorphic computing which is aimed at modeling the biological brain on hardware has gone through decades of research [1], and the ability of the biological brain to carryout rapid parallel computations in real time, in a fault tolerant and power efficient manner is the inspiration behind it [2]
An efficient neuromorphic hardware targeted towards edge application and scalable neuromorphic architecture with large number of synapses requires building small sized neural Processors with low power consumption, efficient neuro-coding scheme, and fault tolerance
To enable scalability while maintaining minimal power consumption and footprint, we presented in our previous work [3] a Three Dimensional Network-on-Chip (3D-NoC) Spiking Neural Network (SNN) based architecture, a different approach from the conventional 2D-NoC which is limited in scalability, and consumes more power with increased latency and foot print, when scaling is attempted

Summary

Introduction

Neuromorphic computing which is aimed at modeling the biological brain on hardware has gone through decades of research [1], and the ability of the biological brain to carryout rapid parallel computations in real time, in a fault tolerant and power efficient manner is the inspiration behind it [2]. An efficient neuromorphic hardware targeted towards edge application and scalable neuromorphic architecture with large number of synapses requires building small sized neural Processors with low power consumption, efficient neuro-coding scheme, and fault tolerance. To enable scalability while maintaining minimal power consumption and footprint, we presented in our previous work [3] a Three Dimensional Network-on-Chip (3D-NoC) SNN based architecture, a different approach from the conventional 2D-NoC which is limited in scalability, and consumes more power with increased latency and foot print, when scaling is attempted. We present the architecture and design of a spiking neuron processor core described in Fig 1 suitable for the 3D-NoC based SNN architecture. Future works towards realizing the 3D-NoC SNN architecture will require integrating the spiking neuron processor core into it, and exploring applications that will leverage the architecture

Methodology

Findings

Result