On the construction of small fully testable circuits with low depth

Abstract

Compact area, low delay and good testability properties are important optimization goals in the synthesis of circuits for Boolean functions. Unfortunately, these goals typically contradict each other. Multi-level circuits are often quite small but can have a long delay, due to their unbounded number of levels. On the other hand, circuits with low depth guarantee low delay but are often larger regarding the area requirements. A different optimization goal is good testability which can usually only be achieved by additional hardware overhead. In this paper we propose a synthesis technique that allows to trade-off between area and delay. Moreover, the resulting circuits are 100% testable under the stuck-at fault model. The proposed approach relies on the combination of 100% testable circuits derived from binary decision diagrams and 2-SPP networks. Full testability under the stuck-at fault model is proven and experimental results show the trade-off between area and depth.