Abstract
A two-dimensional non-planar device simulator for poly-Si TFT is developed, in which the influences of trapped charges and carrier scattering within the grain boundary are incorporated into Poisson's equation and drift-diffusion current formulations, respectively. With this simulator, the I-V characteristics of poly-Si TFT devices can be characterized. Thin-film transistors on polycrystalline silicon were fabricated for testing. Excellent agreement between the simulated results and the experimental data has been obtained. Some TFT characteristics, such as the ‘pseudo-subthreshold’ region, the activation energy and the barrier height are investigated and elucidated by our simulator. Finally, making use of this simulator, we have investigated the effects of poly-Si film and gate oxide thickness on the TFT I-V characteristics; the simulated results predict that scaling down the oxide thickness will drastically improve the driving capability by reducing the grain potential barrier.
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