On mapping parallel algorithms into parallel architectures

Abstract

The mapping problem arises when the communication structure of a parallel algorithm differs from the interconnection architecture of the intended parallel machine ( topological variation). This problem is compounded when the number of processes required by the algorithm exceeds the number of processors available in the architecture ( cardinality variation). In this paper, we present a solution to the mapping problem when there are topological and cardinality variations for a commonly used class of parallel interconnection structures. This class includes, for example, shuffle-exchange networks, hypercubes, square meshes, linear systolic arrays, cube-connected cycles, and complete binary trees. We illustrate this solution by presenting and evaluating mappings from two-dimensional and linear systolic arrays into tree architectures, and from tree algorithms into shuffle-exchange networks.