On-chip triple-error correction and quadruple-error detection ECC structure for ultra-large, single-chip memories

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Soft errors resulting from alpha-particle strikes are one of the major factors that reduces the reliability of memory chips. One way to improve reliability of memory chips is to employ an on-chip error-correcting code (ECC) structure. This paper presents a triple-error correcting and quadruple-error detecting (TEC–QED) code, that is capable of correcting three and detecting four soft errors, simultaneously. The TEC–QED code design is based on odd-weight-column SEC–DED code in conjunction with the parity technique. Results show that timing overhead of less than 11 ns can be expected. The proposed code improves the mean time between failure (MTBF) by a factor of 210%, when compared to DEC APC, and by a factor of 31%, when compared to the interleaved SEC code.