Abstract
Process variations during manufacturing lead to differences in the performance of the chips. In order to better utilize the performance of the chips, it is necessary to perform maximum operation frequency () tests to place the chips into different speed bins. For most tests, significant efforts are put in place to reduce test cost and improve binning accuracy; e.g., our conference paper published in ICICM 2017 presents a novel binning sensor for low-cost and accurate speed binning. However, by promoting chips placed at the lower bins, because of conservative binning, into higher bins, the overall profit can greatly increase. Therefore, this paper, extended based on a conference paper, presents a novel and adaptive methodology for speed binning, in which the paths impacting the speed bin of a specific IC are identified and adapted by our proposed on-chip Binning Checker and Binning Adaptor. As a result, some parts at a bin margin can be promoted to higher bins. The proposed methodology can be used to optimize the yield of a digital circuit when it has redundant timing in clock tree, and it can be integrated into current tests with low extra cost. The proposed adaptive system has been implemented and validated on five benchmarks from ITC, ISCAS89, and OpenSPARCT2 core on 28 nm Altera FPGAs. Measurement results show that the number of higher bin chips is improved by 7–16%, and our cost analysis shows that the profit increase is between 1.18% and 3.04%.
Highlights
Process variation during manufacturing impacts the oxide thickness, threshold voltage, etc. of the transistor in integrated circuits, resulting in path delay fluctuations [1,2]
The Integrated Circuits and Microsystems (ICICM) 2017 paper [29] only focuses on a novel binning sensor for low-cost and accurate speed binning, while this paper focuses on promoting chips placed in the lower bins into higher bins
If we define the Yield Optimization Rate as the probability of successfully promoting a device to the higher bin, it can be calculated as Equation (1), where m is the number of unselected paths with a probability of silicon failure belonging to Case 1, and n is the number of selected paths with a probability of being unadaptable belonging to
Summary
Process variation during manufacturing impacts the oxide thickness, threshold voltage, etc. of the transistor in integrated circuits, resulting in path delay fluctuations [1,2]. Efficiently and accurately Fmax tests are required to prevent high-performance chips from being placed into low bins. An Fmax test based on on-chip sensors has a lower requirement for high-end external equipment than a functional test [38], and it takes less time than a structural test. This type of test has gradually become popular in recent years. Based on the Fmax test results, the proposed system can improve the Fmax yield and increase the overall profit by promoting chips from lower speed bins to higher speed bins.
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